Technical Field
The present invention relates to co-fabricating a vertical field effect transistor (VFET) structure with a vertical diode, and more particularly to the co-integration of a VFET and companion p-n vertical diode on the same substrate.
Description of the Related Art
A Field Effect Transistor (FET) typically has a source, a channel, and a drain, where current flows from the source to the drain, and a gate that controls the flow of current through the channel. Field Effect Transistors (FETs) can have a variety of different structures, for example, FETs have been fabricated with the source, channel, and drain formed in the substrate material itself, where the current flows horizontally (i.e., in the plane of the substrate), and finFETs have been formed with the channel extending outward from the substrate, but where the current also flows horizontally from a source to a drain. The channel for the finFET can be an upright slab of thin rectangular Si, commonly referred to as the fin with a gate on the fin, as compared to a MOSFET with a single gate in the plane of the substrate. Depending on the doping of the source and drain, an n-FET or a p-FET may be formed.
Examples of FETs can include a metal-oxide-semiconductor field effect transistor (MOSFET) and an insulated-gate field-effect transistor (IGFET). Two FETs also may be coupled to form a complementary metal oxide semiconductor (CMOS), where a p-channel MOSFET and n-channel MOSFET are coupled together.
As MOSFETs are scaled to smaller dimensions, designs and techniques are employed to improve device performance. Vertical transistors are attractive candidates for scaling to smaller dimensions. In vertical transistors, the source/drain regions are arranged on opposing ends of a vertical channel region. Vertical transistors may provide higher density scaling and allow for relaxed gate lengths to better control device electrostatics without sacrificing the gate contact pitch size.